1. Field of the Invention
The present invention relates to a flash memory comprising a memory array in which a bit line is shared by memory cells, and a program verify method for the same.
2. Description of the Background Art
In conventional non-volatile memories, such as a flash memory, an EEPROM and the like, a floating gate type memory cell which uses an electrical conductor material (e.g., polysilicon, etc.) as data storage means is employed. In recent years, an NROM (Nitride Read-Only Memory) type memory cell which uses an insulator ONO film (a composite structure of a nitride film and oxide films) has attracted attention as data storage means in order to improve the degree of integration and reliability.
When the NROM type memory cell is used to construct a memory array, a virtual ground array technology is employed in which a bit line is shared by memory cells neighboring each other. In the virtual ground array type memory array, a bit line shared by memory cells neighboring each other in a direction of a word line (the bit line is hereinafter referred to as a diffused bit line) is provided in addition to the memory cell and the word line (see FIG. 2 described below). By sharing the bit line in this manner, the NROM type memory cell can be used to construct a highly integrated memory array.
A program process and an erase process with respect to the NROM type memory cell will be described. By externally applying a certain voltage to the NROM type memory cell, a channel current flows between a drain and a source, so that hot electrons can be injected into the memory cell. Also, by externally applying another voltage to the memory cell, hot holes generated by an interband tunnel effect can be injected into the memory cell. The memory cell into which hot electrons have been injected goes to a high threshold state, while the memory cell into which hot holes have been injected goes to a low threshold state. Hereinafter, the high threshold state is referred to as a programmed state, while the low threshold state is referred to as an erased state. The programmed state and the erased state are associated with, for example, a 0-storing state and a 1-storing state, respectively.
A process of transitioning a memory cell from the programmed state to the erased state is generally executed with respect to a plurality of memory cells simultaneously. In contrast, a process of transitioning a memory cell from the erased state to the programmed state is executed for each memory cell individually. Hereinafter, a process of simultaneously transitioning a plurality of memory cells into the erased state is referred to as an erase process, while a process of transitioning a designated memory cell(s) among a plurality of memory cells into the programmed state is referred to as a program process. The program process and the erase process are executed mainly by applying a pulse having a predetermined voltage level to a drain-side diffused bit line while applying a voltage having a predetermined level to a desired word line (gate line). Also in the program process and the erase process, after applying a pulse, a verify process is executed to determine whether or not a state of a memory cell is changed. Particularly, a verify process in a program process is referred to as a program verify process.
A source-side read scheme is widely known as a method of reading out data from a virtual ground array type memory array. In the source-side read scheme, all diffused bit lines are temporarily connected to a ground potential before selection of a memory cell to be read out, and thereafter, are controlled to be in a high impedance state. A gate bias is applied via a word line to the gate of the memory cell to be read out, a read drain bias (e.g., about 2 V) is applied to the drain thereof, and a source-side diffused bit line is connected to a sense amplifier. By applying these voltages, a current is caused to flow through the memory cell (hereinafter, the current is referred to as a cell current). The cell current flows through the source-side diffused bit line. The sense amplifier compares the cell current flowing through the source-side diffused bit line with a reference cell current obtained by another means. When the cell current is larger than the reference cell current, data read from the memory cell is determined to be 1, and when otherwise, the data is determined to be 0.
Hereinafter, a memory cell M, and a memory cell M′ which is one of the memory cells connected to the same word line as that to which the memory cell M is connected, the memory cell M′ being disposed on a source side (read bit line side) of the memory cell M, will be discussed. The number of memory cells disposed between the memory cell M (exclusive) and the memory cell M′ (inclusive) is referred to as an offset. A memory cell which is located at an offset of a predetermined number n or less (where n is a positive integer) from the memory cell M is referred to as a neighbor cell. For example, a memory cell M1 which shares its source-side diffused bit line with the memory cell M is called a 1st-offset neighbor cell with respect to the memory cell M. A memory cell M2 which shares its drain-side diffused bit line with the memory cell M1 is referred to as a 2nd-offset neighbor cell with respect to the memory cell M (see FIG. 2 described below)
Note that a detailed operation of an NROM type memory cell is described in, for example, International Publication WO99/07000, U.S. Pat. Nos. 5,768,192, 6,011,725 and the like. The virtual ground array technology is described in U.S. Pat. Nos. 5,963,465, 5,204,835, and U.S. Pat. No. 5,151,375. The source-side read scheme is described in detail in U.S. Pat. No. 6,134,156.
However, a flash memory having the virtual ground array type memory array has a problem that a neighbor cell effect occurs in the memory array, resulting in a reduction in reliability. The memory cell M included in the virtual ground array type memory array shares its source-side diffused bit line with the 1st-offset neighbor cell M1. Since the neighbor cell M1 is connected to the same word line as that of the memory cell M, the neighbor cell M1 as well as the memory cell M are selected when data is read from the memory cell M. Therefore, when data is read from the memory cell M, a portion of a cell current of the memory cell M flows into the neighbor cell M1, so that a cell current which is detected by the sense amplifier connected to the source-side diffused bit line of the memory cell M, is reduced. This phenomenon is called a loss of a cell current due to neighbor cell(s) (hereinafter also simply referred to as a neighbor cell effect).
When the neighbor cell effect occurs, an amount of the cell current detected by the sense amplifier varies depending on states of neighbor cell(s) even when the memory cell to be read out has the same state. More specifically, the amount of a cell current detected by a sense amplifier varies depending on the number of consecutive erased-state neighbor cells counted from a 1st-offset neighbor cell. As an example, a first case in which the above-described number is 0 (i.e., the 1st-offset neighbor cell is in the programmed state) is compared with a second case in which the number is 3 (i.e., 1st- to 3rd-offset neighbor cells are in the erased state and a 4th-offset neighbor cell is in the programmed state). In this case, the amount of a current flowing through the neighbor cell is larger in the second case, assuming that the memory cell to be read out is in the same state. Therefore, the amount of a cell current detected by the sense amplifier is smaller in the second case.
The phenomenon that a cell current varies depending on the states of neighbor cell(s), also occurs in a program verify process. Therefore, the number of times of applying a pulse to a memory cell so that the memory cell is transitioned to the programmed state, i.e., a threshold of the memory cell, also varies depending on the states of neighbor cell(s). For example, when a memory cell is transitioned to the programmed state in the first and second cases, a cell current detected by a sense amplifier in a program verify process is smaller in the second case than in the first case. Therefore, in the second case, the number of times of applying a pulse is erroneously determined to be smaller than that of the first case.
Since the number of times of applying a pulse varies depending on the states of neighbor cell(s), the threshold of a memory cell in the programmed state is distributed in a wide range of a lower level region than an ideal one. Therefore, a read margin is decreased or the reliability of a flash memory is reduced. Therefore, it is recognized that it is important to eliminate an influence of the neighbor cell effect for a flash memory comprising a virtual ground array type memory array.